The present inventions are related to systems and methods for transferring information, and more particularly to systems and methods for reducing the effects of latency in data detection processes.
Various products including hard disk drives typically utilize a read channel device that provides an ability to retrieve information from a medium in one format, and provide it to a recipient in a digital data format. Such read channel devices include an analog to digital converter along with a data detector circuit implemented such that data dependencies may be used to process received information. For example, the information provided from the data detector may be used to determine the sampling points of the analog to digital converter. Turning to FIG. 1, an exemplary read channel device 100 is depicted that utilizes previously detected information to control sampling processes related to later received information. Read channel device 100 receives an analog input 103 which is processed using a continuous time filter 105. A filtered output 107 is provided to an analog to digital converter 110 that converts analog input 103 to a digital input 115 that is filtered using a digital finite impulse response filter 120. A filtered digital output 122 is provided to a data detector 125 which processes filtered digital output 122 and provides decisions indicative of a data output 127. When the error rate is reasonably low, data output 127 reflects data originally provided to a storage medium from which data input 103 is derived.
In addition, filtered digital output 122 is provided to a delay element 160 that operates to delay digital filtered output 122 to reflect the delay incurred by passing through data detector 125. The output of delay element 160 is effectively a filtered version of the output of analog to digital converter 110. Output 127 from data detector 125 is provided to an equalization target filter 130. The output of equalization target filter 130 is effectively what the filtered output of analog to digital converter 110 would have been in the absence of channel imperfections. The difference from what you want to receive (i.e., the output of equalization target filter 130) and what you received (i.e., the output of delay block 160) is created using a summation circuit 135. The output of summation circuit 135 is an error signal 137. In addition, a slope detection circuit 140 receives output 127 and determines a slope signal 142. A timing error detector circuit 145 combines slope signal 142 and error signal 137 to calculate a phase error adjustment which is reflected in a timing error signal 147. Timing error signal 147 is filtered by a loop filter 150 and the filtered value is provided to a phase mixer circuit 155. Phase mixer circuit 155 receives the output of loop filter 150 and provides a signal that controls the sampling phase of analog to digital converter 110.
The feedback of information from data detector 125 to analog to digital converter 110 provides for more accurate data detection processes, but the feedback loop incurs some level of latency. As the density of storage applications continues to increase, there is a potential that the latency incurred due to the feedback loop may become significant and may reduce the error rate performance of a read channel device. Further, feedback loop latency may become a gating factor to developing storage applications with increased data density and/or lower signal to noise ratios.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for performing data detection processes.